gate delay造句
例句與造句
- Trigger gate delay
觸發(fā)門脈沖延遲 - The problem in high speed signal process , such as parasitic parameter and gate delay is also the difficulty hi the research
生成高速，穩(wěn)定的時(shí)鐘信號是本課題的目標(biāo)。高速信號處理所遇到的常見問題，如寄生參數(shù)，門電路延遲是設(shè)計(jì)難點(diǎn)。 - Due to the subtle error among different manufacturing equipment , the gate delay of circuits is different and varies in a given scope , which induces the time uncertainty of the waveform
由于制造設(shè)備本身存在微小誤差，具體門的延時(shí)并不相同，而是在一定范圍內(nèi)變化，引起波形變化的時(shí)間不確定。 - This paper constructs a stable rlc interconnect model based on the first three moments of the node admittance , and discusses its application to interconnect delay and logic gate delay estimation
摘要基于rlc互連樹節(jié)點(diǎn)導(dǎo)納的低階矩構(gòu)建了一種穩(wěn)定的互連模型，并討論了它在互連樹延時(shí)和邏輯門延時(shí)估計(jì)中的應(yīng)用。 - When the silicon technology comes to deep sub - micron level , the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency , the allowable errors become smaller , and the influence of the transmission delay gets bigger , which increase the difficulty of the circuit design
在深亞微米制造技術(shù)中，芯片互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時(shí)序容差變小，傳輸延遲的影響加大，設(shè)計(jì)工作難度增加。 - It's difficult to find gate delay in a sentence. 用gate delay造句挺難的
- An algorithm of path - based timing optimization by buffer insertion is presented . the algorithm adopts a high order model to estimate interconnect delay and a nonlinear delay model based on look - up table for gate delay estimation . and heuristic method of buffer insertion is presented to reduce delay . the algorithm is tested by industral circuit case . experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied
提出了一種基于路徑的緩沖器插入時(shí)延優(yōu)化算法,算法采用高階模型估計(jì)連線時(shí)延,用基于查表的非線性時(shí)延模型估計(jì)門延遲.在基于路徑的時(shí)延分析基礎(chǔ)上,提出了緩沖器插入的時(shí)延優(yōu)化啟發(fā)式算法.工業(yè)測試實(shí)例實(shí)驗(yàn)表明,該算法能夠有效地優(yōu)化電路時(shí)延,滿足時(shí)延約束 - In this paper an fault simulator for iddt testing is presented , which can detect concurrently the multi - faults . due to the subtle error among equipment manufacturing , the gate delays of circuits are not the same but range within limits . which induces the uncertainty of the waveform transforming time
本文從故障激活的條件入手,利用五值邏輯,對瞬態(tài)電流測試中的延時(shí)變化進(jìn)行波形分析和波形計(jì)算,采用并發(fā)模擬算法,編程實(shí)現(xiàn)了一個(gè)iddt測試的故障模擬器。實(shí)際電路中由于制造工藝的限制,邏輯門的延時(shí)并不相同,而是在一定范圍內(nèi)變化,引起波形變化的時(shí)間不確定。